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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: june 2004 document no. 522 - 28 - 05 data sheet gs1545 features ? smpte 292m compliant 1.485 and 1.485/ 1.001gb/s operation integrated adaptive cable equalizer integrated adjustment-free reclocker 1:20 serial to parallel conversion selectable reclocked serial output analog/digital input mux carrier detect lock detect input jitter indicator (iji) cable length indication maximum cable length adjust 20 bit output 74.25mhz or 74.25/1.001mhz clock output pb-free and green single +5.0v power supply minimal component count for hd sdi receive solutions applications smpte 292m serial digital interfaces for video cameras, camcorders, vtrs, signal gener ators, portable equipment, and nles. description the gs1545 is a high performance integrated equalizing receiver designed for hdtv component signals, conforming to the smpte 292m standard. the gs1545 includes adjustment free adaptive cable equalization, clock and data recovery, and serial to parallel conversion. the equalizer stage features dc restoration for immunity to the dc content in pathological test patterns. the clock and data recovery stage was designed to auto- matically recover the embedded clock signal and re-time the data from smpte 292m com pliant digital video signals. there is also a selectable recl ocked serial data output and the ability to bypass the reclocker stage. a unique feature, input jitter indi cator (iji), is included for robust system design. this f eature is used to indicate excessive input jitter before the chip mutes the outputs. the serial to parallel conver sion stage provides 1:20 s/p conversion the gs1545 uses the go1515 external vco connected to the internal pll circuitry to achieve ultra low noise pll performance. simplified block diagram ordering information part number package temperature pb-free and green gs1545-cqr 128 pin mqfp 0c to 70c no GS1545-CQRE3 128 pin mqfp 0c to 70c yes reclocker core equalizer core s/p converter buffer ddo_en ddo ddo data_out[19:0] ddi ddi_v tt (opt) ddi a/d sdi sdi analog- digital mux & buffer ddoint ddoint pclk_out hd-linx ? gs1545 hdtv serial digital equalizing receiver
gennum corporation 522 - 28 - 05 2 of 19 gs1545 functional block diagram absolute maximum ratings t a = 25c, unless otherwise shown. parameter value supply voltage (v s )5.5v input voltage range (any input) v ee ? 0.5 < v in < v cc + 0.5 operating temperature range 0c t a 70c storage temperature range -40c t s 150c power dissipation (v cc = 5.25v) 2.1w lead temperature (soldering 10 seconds) 260c input esd voltage 1000v junction temperature 125c pll_lock reclocker core s/p converter core buffer ddo_en bypass ddo ddo data_out[19:0] ddi ddi_v tt (opt) ddi pclk_out mute phase detector charge pump phase lock logic go1515 bypass mux lfs lfs plcap plcap iji vco lfa equalizer core agc eq core dc restore cable length indicator maximum cable length adjust carrier detect a/d analog- digital mux & buffer buffer cli cd mcladj sdi sdi ddoint+ ddoint-
gennum corporation 522 - 28 - 05 3 of 19 gs1545 dc electrical characteristics v cc = 5v, v ee = 0v, t a = 0c to 70c unless otherwise shown, data rate = 1.485gb/s. parameter conditions symbol min typ max units test level positive supply voltage operating range v cc 4.75 5.00 5.25 v 3 power consumption v cc = 5; t a = 25c p d - 1270 1535 mw 5 supply current v cc = 5 i s - 235 295 ma 1 output cm voltage (ddo, ddo )v cm 3.4 3.9 4.30 v 5 input dc voltage (ddi, ddi ) internal bias voltage 3.7 4.0 4.2 v 1 input dc voltage (sdi, sdi ) internal bias voltage 2.4 2.65 2.80 v 1 serial inputs (ddi, ddi ) differential mode t a = 25c v sid 100 - 800 mv 3 common mode t a = 25c v cm 2.5+v sid/2 -v cc -v sid/2 v3 high level input voltage (a/d , bypass ) v cc = 5, t a = 25c v ih 2.0 - - v 3 low level input voltage (a/d , bypass ) v cc = 5, t a = 25c v il --0.8v3 high level output voltage (d[19:0], pclk) v cc = 5, i source = 1.0ma v oh 2.4 - 3.0 v 1 low level output voltage (d[19:0], pclk) v cc = 5, i sink = 1.0ma v ol --0.4v1 high level output voltage (pll_lock) v cc = 5, i source = 200a v oh 2.4 3.0 - v 1 low level output voltage (pll_lock) v cc = 5, i sink = 500a v ol --0.4v1 low level output voltage (cd ) i sink = 500a v ol --0.4v1 cli dc voltage 1 meter, 800mv p-p input t a = 25c 2.9 3.2 3.6 v 3 cli dc voltage (max cable length) 120 meters, belden 1694a t a = 25c 1.0 1.4 2.3 v 3 mcladj dc voltage 1 meter, 800mv p-p input t a = 25c 3.4 4.1 4.3 v 3 mcladj dc voltage (max cable length) 120 meters, 800mv p-p input t a = 25c 2.9 3.1 3.4 v 3 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltag e with guardbands for supply and temperature ranges using correl ated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test.
gennum corporation 522 - 28 - 05 4 of 19 gs1545 ac electrical characteristics - reclocker stage v cc = 5v, t a = 25c parameter conditions symbol min typ max units test level serial input ? data rate smpte 292m br sdi 1.485/1.001 1.485 - gb/s 3 serial input ? jitter tolerance sinewave modulation (p ? p) j tol 0.5 0.6 - ui 9 phase lock time - asynchronous loop bandwidth approximately 1.4mhz @ 0.2 ui input jitter modulation (lbcont floating). t alock - 120 145 ms 7 phase lock time - synchronous loop bandwidth approximately 1.4mhz @ 0.2 ui input jitter modulation (lbcont floating). t slock -23.2s7 carrier detect response time loop bandwidth approximately 1.4mhz @ 0.2 ui input jitter modulation (lbcont floating). -1214ms7 phase lock/unlock time (1nf plcap) loop bandwidth approximately 1.4mhz @ 0.2 ui input jitter modulation (lbcont floating). 80 - - s 7 digital data output (ddo) ? signal swing v ddo 355 400 480 mv 1 digital data output (ddo) ? rise and fall time t r-ddo , t f-ddo - 160 - ps 7 digital data output (ddo) ? rise and fall time mismatch -30-ps7 digital data output (ddo) ? intrinsic jitter (rms jitter for clean prn 2 23 ? 1 input on ddi/ddi inputs) t ij -10-ps9 loop bandwidth @ 0.2ui jitter modulation lbcont floating 1.2 1.4 1.5 mhz 7 jitter peaking --0.1db7 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply vo ltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/c haracterization data of similar product. 9. indirect test.
gennum corporation 522 - 28 - 05 5 of 19 gs1545 ac electrical characteristics - equalizer stage v cc = 5v, t a = 25c parameter conditions symbol min typ max units test level equalization belden 1694a - 110 - m 3 input resistance (sdi, sdi )-3.2-k ? 7 input capacitance (sdi, sdi )c in -2.0-pf7 ac electrical characteristics - serial to parallel stage v cc = 5v, t a = 25c parameter conditions symbol min typ max units test level parallel output clock frequency smpte 292m p clk_out 74.25/1.001 74.25 - mhz 3 clock pulse width low 15pf load t pwl 7-6.1ns7 clock pulse width high 15pf load t pwh 6-6.4ns7 output signal rise/fall time 15pf load t r , t f - 2.70 3.60 ns 7 output signal rise/fall time mismatch 15pf load t rfm - 1.00 1.60 ns 7 output setup time 15pf load t od 55.5-ns7 output hold time 15pf load t oh 6.2 7.1 - ns 7 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply vo ltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/c haracterization data of similar product. 9. indirect test.
gennum corporation 522 - 28 - 05 6 of 19 gs1545 pin connections nc nc pclk_v ee pclk_v cc pclk_out sp_v ee sp_v ee sp_v cc sp_v cc nc nc nc nc nc nc nc nc ddo_v cc ddo_en ddo_v ee ddo ddo eqo_v cc nc nc eqo_v ee cd nc nc nc nc cli nc mcladj nc nc nc nc nc nc nc nc nc nc lfa_v cc lfa lbcont lfa_v ee dft_v ee nc nc dm dm lfs nc nc nc lfs iji nc nc vco nc vco nc plcap nc nc plcap nc pll_lock nc nc nc nc data_out[19] data_out[18] data_out[17] data_out[16] data_out[15] data_out[14] nc nc data_out[13] data_out[12] data_out[11] data_out[10] nc nc data_out[9] data_out[8] data_out[7] data_out[6] data_out[5] data_out[4] data_out[3] data_out[2] data_out[1] data_out[0] nc nc nc nc bypass ddi_v tt nc ddi ddi pd_v cc a/d pdsub_v ee pd_v ee nc nc nc eqi_v cc nc nc eqi_v ee nc sdi nc sdi nc eqi_v ee nc nc 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 gs1545 top view nc
gennum corporation 522 - 28 - 05 7 of 19 gs1545 pin descriptions number symbol level type description 1, 2, 3, 4, 6, 8, 9, 10, 11, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 37, 38, 39, 40, 51, 52, 57, 58, 65, 66, 67, 68, 69, 70, 71, 77, 78, 82, 83, 84, 87, 88, 90, 92, 94, 95, 97, 99, 100, 101, 102, 103, 104, 107, 114, 115, 116, 118, 119, 121, 123, 125, 127, 128 nc no connect . leave these pins floating. 5 mcladj analog input control signal input . adjusts the maximum amount of cable for the equalizer (from 0m to the maximum cable length). normally the output is muted (latched to the last state) when the set maximum cable length is exceeded. to achieve maxi mum cable length, this pin should be left open (floating). 7 cli analog output status control signal . the cable length indication (cli) signal provides approximate voltage representation of the amount of cable being equalized. 12 cd digital output status signal. the carrier detect indicator is used as an output status signal. when the cd output is low, the carrier is present and the data output is active. when the cd output is high, the carrier is not present and the data output is muted (latched to the last state). this indicates that the maximum cable length as set by mcladj has been reached. 13 eqo_v ee power input negative supply . most negative power supply connection for equalizer output buffer stage. 16 eqo_v cc power input positive supply . most positive power supply connection for equalizer output buffer stage. 17, 18 ddo, ddo ecl/pecl compatible output digital data output . differential serial outputs. 50 ? pull up resistors are included on chip. note that these outputs are not cable drivers. ensure that the trace length between the gs1545 and the gs1508 cable driver is kept to a minimu m and that a pcb trace characteristic impedance of 50 ? is maintained between the gs1508 and the gs1545. 50 ? end termination is recommended. 19 ddo_v ee power input negative supply . most negative power supply connection for serial data output stage. 20 ddo_en power input control signal input . used to enable or disable the serial output stage. if a loop through function is not requ ired, then this pin should be tied to the most positive power supply voltage. when ddo_en is tied to the most negative power supply voltage, the ddo, ddo outputs are enabled. when ddo_en is tied to the most positive power supply voltage, the ddo, ddo outputs are disabled. 21 ddo_v cc power input positive supply . most positive power supply connection for serial data output stage. 30, 31 sp_v cc power input positive supply. most positive power supply connection for serial to parallel converter stage.
gennum corporation 522 - 28 - 05 8 of 19 gs1545 32, 33 sp_v ee power input negative supply . most negative power supply connection for the parallel output stage. 34 pclk_out ttl output output clock. the device uses pclk_out for clocking the output data stream from data_out[19:0]. this clock is also used to clock the data into the gs1500 hdtv deformatter or gs1510 deformatter. 35 pclk_v cc power input positive supply. most positive supply connection for parallel clock output stage. 36 pclk_v ee power input negative supply. most negative power supply connection for parallel clock output stage. 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 53, 54, 55, 56, 59, 60, 61, 62, 63, 64 data_out[19:0] ttl output parallel data output bus. the device outputs a 20 bit parallel data stream running at 74.25 or 74 .25/1.001mhz on data_out[19:0]. data_out[19] is the msb and data_out[0] is the lsb. 72 lfa_v cc power input positive supply . loop filter most positive power supply connection. 73 lfa analog output control signal output. control voltage for go1515 vco. 74 lbcont analog input control signal input . used to provide electronic control of loop bandwidth. 75 lfa_v ee power input negative supply . loop filter most negative power supply connection. 76 dft_v ee power input most negative power supply connection - enables the jitter demodulator functionality. this pin should be connected to ground. if left floating, the dm function is disabled resulting in a current saving of 340a. 79, 80 dm, dm analog output test signal . used for manufacturing test only. these pins must be floating for normal operation. 81, 85 lfs, lfs analog input loop filter connections . 86 iji analog output status signal output . approximates the amount of excessive jitter on the incoming ddi and ddi input. 89 vco analog input control signal input . input pin is ac coupled to ground using a 50 ? transmission line. 91 vco analog input control signal input. voltage controlled oscillator input. this pin is connected to the output pin of the go1515 vco. this pin must be connected to the go1515 vco output pin via a 50 ? transmission line. 93, 96 plcap, plcap analog input control signal input . phase lock detect time constant capacitor. 98 pll_lock ttl output status indicator signal . this signal is a combinat ion (logical and) of the carrier detect and phase lock signals. when input is present and pll is locked, the pll_lock goes high and the outputs are valid. when the pll_lock output is low the data output is muted (latched at the last state). pll_lock is independent of the bypass signal. 105 bypass ttl input control signal input . selectable input that controls whether the input signal is reclocked or passed through the chip. when bypass is high; the input signal is reclocked. when bypass is low; the input signal is passed through the chip and not reclocked. muting does not effect bypassed signal. pin descriptions (continued) number symbol level type description
gennum corporation 522 - 28 - 05 9 of 19 gs1545 106 ddi_v tt analog input bias input. selectable input for interfacing standard ecl outputs requiring 50 ? pull down to v tt power supply for a seamless interface. see typical application circuit for recommended circuit application. 108, 109 ddi, ddi differential ecl/pecl input digital data input signals. digital input signals from a gs1504 equalizer or hd crosspoint switch. because of on chip 50 ? termination resistors, a pcb trace characteristic impedance of 50 ? is recommended. 110 pd_v cc power positive supply . phase detector most positive power supply connection. 111 a/d ttl input control signal input. used to select between the sdi/sdi input or ddi/ddi input. when a/d is high; the sdi/sdi input is selected. when a/d is low; the ddi/ddi input is selected. 112 pdsub_v ee power input substrate connection . connect to phase detector?s most negative power supply. 113 pd_v ee power input negative supply. phase detector most negative power supply connection. 117 eqi_v cc power input positive supply . most positive power supply connection for serial input stage. 120, 126 eqi_v ee power input negative supply. most negative power supply connection for serial input stage. 122, 124 sdi, sdi analog input serial data input signals . ac coupled termination is recommended. single ended to differential conversion is also feasible. the sdi and sdi input is selected when the a/d signal is high. ensure that the trace length between the input connector and the gs1545 ic is kept to a minimum and that a pcb trace characteristic impedance of 75 ? is maintained between the connector and the device. pin descriptions (continued) number symbol level type description
gennum corporation 522 - 28 - 05 10 of 19 gs1545 input/output circuits fig. 1 ddi/ddi input circuit fig. 2 vco/vco input circuit fig. 3 dm/dm output circuit fig. 4 plcap/plcap output circuit fig. 5 lfa circuit fig. 6 lfs output circuit pd_v ee ddi_v tt pd_v cc ddi ddi 50 50 20k 5k pd_v ee pd_v cc vco vco 50 10k 5k 5k 10k 31p dft_v ee 10k 10k dm dm 85a pd_v cc pd_v ee 20k 10k plcap plcap 100a pd_v cc lfa_v ee lfa_v cc 40 40 500 5ma 100a lfa lfa_v ee lfa_v cc 25k 400a lfs
gennum corporation 522 - 28 - 05 11 of 19 gs1545 fig. 7 lfs input circuit fig. 8 pll_lock output circuit fig. 9 iji output circuit fig. 10 a/d input circuit fig. 11 bypass circuit fig. 12 lbcont circuit fig. 13 d[19:0] output circuit fig. 14 pclk output circuit lfa_v ee lfa_v cc 100a 100a 100a 100a 10k 5k lfs pd_v ee pd_v cc 10k pll_lock pd_v cc iji 10k 5k v cc 30k a pd_v ee pd_v e e 20k 16k 100a pd_v cc a/d + - 2.4v pd_v ee pd_v cc 16k 100a bypass v = 2.4v + - lfa_v ee lfa_v cc 20k lbcont 5k sp_v ee sp_v cc 27k 100 0.1uf d[19:0] pclk_v ee pclk_v cc 27k 100 pclk
gennum corporation 522 - 28 - 05 12 of 19 gs1545 fig. 15 ddo_en circuit fig. 16 equalizer input circuit fig. 17 mcladj equivalent circuit fig. 18 serial (ddo) output stage circuit fig. 19 cli output circuit fig. 20 cd circuit ddo_v ee ddo_v cc 2k 20k ddo_en eqi_v ee eqi_v cc 6k sdi 7k sdi 6k 7k rc eqi_v cc mcladj 40k 42 + - eqi_v ee 50 50 ddo ddo ddo_v ee ddo_v cc 10k 10k eqo_v cc cli - + 10k 20k output stage mute control eqo_v cc cd eqo_v ee
gennum corporation 522 - 28 - 05 13 of 19 gs1545 detailed description the gs1545 is a single standard equalizing receiver for serial digital hdtv signals at 1.485gb/s and 1.485/1.001gb/s. unique slew phase lock loop (s-pll): a unique feature of the gs1545 is the innovative slew phase lock loop (s-pll). when a st ep phase change is applied to the pll, the output phase gains constant rate of change with respect to time. this b ehaviour is termed slew. figure 21 shows an example of input and output phase variation over time for slew and linear (conventional) plls. since the slewing is a nonlinear behavior, the small signal analysis cannot be done in the same way as the standard pll. however, it is still possible to plot input jitter transfer characteristics at a constant input jitter modulation. fig. 21 pll characteristics slew plls offer several advant ages such as excellent noise immunity. because of the infinite bandwidth for an infinitely small input jitter modulation (o r jitter introduced by vco), the loop corrects for that immediately thus the small signal noise of the vco is cancelled. the gs1545 uses a very clean, external vco called the go1515 ( refer to the go1515 data sheet for details ). in addition, the bi-level digital phase detector provides constant loop bandwidth that is predominantly independent of the data transition density. the loop bandwidth of a conventional tri-stable charge pump drops with reducing data transitions. during pathological signals, the da ta transition density reduces from 0.5 to 0.05, but the slew plls performance essentially remains unchanged. because most of the pll circuitry is digital, it is more like other digital systems which are generally more robust than their analog counterparts. additionally, signals like dm/dm which represent the internal functionality can be generated without adding additional ar tifacts. thus, system debugging is also possible with these features. the complete slew pll is made up of several blocks including the phase detector, the charge pump and an ex ternal voltage controlled oscillator (vco). digital input buffer the input buffer is a self-biased circuit. on-chip 50 ? termination resistors provide a seamless interface for other hd-linx? products such as the gs1504 adaptive cable equalizer. the digital input is selected by applying a logic low to the a/d pin. analog input the hd serial data signal may be connected to the input pins (sdi/sdi ) in either a differential or single ended configuration. ac coupling of the inputs is recommended, as the sdi and sdi inputs are internally biased at approximately 2.7 volts. the input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. in addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. the analog input is selected by applying a logic high to the a/d pin. the edge energy of the equalized signal is monitored by a detector circuit which produces an error signal cor- responding to the difference between the desired edge energy and the actual edge energy. this error signal is integrated by an internal agc filter capacitor providing a steady control voltage for the gain stage. as the frequency response of the gain stage is automatically varied by the application of negat ive feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. the equalized signal is al so dc restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to ac coupling. phase detector the phase detector portion of the slew pll used in the gs1545 is a bi-level digital phase detector. it indicates whether the data transition occurred before or after with respect to the falling edge of the internal clock. when the phase detector is locked, the data transition edges are aligned to the falling edge of the clock. the input data is then sampled by the rising ed ge of the clock, as shown in figure 22. in this manner, the allowed input jitter is 1ui p-p in an ideal situation. however, due to setup and hold time, the gs1545 typically achieves 0.5ui p-p input jitter tolerance without causing any errors in this block. when the 0.2 0.1 0.0 input output slew pll response phase (ui) 0.2 0.1 0.0 input output linear (conventional) pll response phase (ui)
gennum corporation 522 - 28 - 05 14 of 19 gs1545 signal is locked to the internal clock, the control output from the phase detector is refres hed at the transition of each rising edge of the data input. during this time, the phase of the clock drifts in one direction. fig. 22 phase detector characteristics during pathological signals, the amount of jitter that the phase detector will add can be calculated. by choosing the proper loop bandwidth, the amount of phase detector induced jitter can also be limited. typically, for a 1.41mhz loop bandwidth at 0.2ui input jitter modulation, the phase detector induced jitter is about 0.015uip-p. this is not very significant, even for the pathological signals. charge pump the charge pump in a slew pll is different from the charge pump in a linear pll. there are two main functions of the charge pump. one function is to hold the frequency information of the input data. this information is held by c cp1 , which is connected between lfs and lfs . the other capacitor, c cp2 between lfs and lfa_gnd is used to remove common mode noise. both c cp1 and c cp2 should be the same value. the second function of the charge pump is to provide a binary control voltage to the vco depending upon the phase detector output. the output pin, lfa controls the vco. internally there is a 500 ? pull-up resistor, which is driven with a 100a current called p . another analog current f , with 5ma maximum drive proportional to the voltage across the c cp1, is applied at the same node. the voltage at the lfa node is v lfa_vcc - 500( p + f ) at any time. because of the integrator, f changes very slowly whereas p could change at the positive edge of the data transition as often as a clock period. in the locked position, the average voltage at the lfa (v lfa_vcc ? 500( p /2+ f ) is such that vco generates frequency ?, equal to the data rate clock frequency. since p is changing all the time between 0a and 100a, there will be two levels generated at the lfa output. vco the go1515 is an external hybrid vco, which has a centre frequency of 1.485ghz and is also guaranteed to provide 1.485/1.001ghz within the control voltage (3.1v ? 4.65v) of the gs1545 over process, po wer supply and temperature. the go1515 is a very clean frequency source and, because of the internal high q resonator, it is an order of magnitude more immune to external noise as compared to on-chip vcos. the vco gain, k?, is nominally 16mhz/v. the control voltage around the average lfa voltage will be 500 x p /2. this will produce two frequenci es off from the centre by ?=k? x 500 x p /2. lbcont the lbcont pin is used to adjust the loop bandwidth by externally changing the internal charge pump current. for maximum loop bandwidth, connect lbcont to the most positive power supply. for medium loop bandwidth, connect lbcont through a pull-up resistor (r pull-up ). for low loop bandwidth, leave lbcont floating. the formula below shows the loop bandwidth for various configurations. where lbw nominal is the lo op bandwidth when lbcont is left floating. loop bandwidth optimization since the feed back loop has only digital circuits, the small signal analysis does not appl y to the system. the effective loop bandwidth scales with the amount of input jitter modulation index. phase lock the phase lock circuit is used to determine the phase locked condition. it is done by generating a quadrature clock by delaying the in-phase clock (the clock whose falling edge is aligned to the data transition) by 166ps (0.25ui at 1.5ghz) with the tolerance of 0.05ui. when the pll is locked, the falling edge of the in-phase clock is aligned with the data edges as shown in figure 23. the quadrature clock is in a logic high state in the vicinity of input data transitions. the quadrature clock is sampled and latched by positive edges of the data transitions. the generated signal is low pass filtered with an rc network. the r is an on-chip 20k ? resistor and c pl is an external capacitor (recommended value 10nf). the time constant is about 67s, or more than a video line. in-phase clock input data with jitter output data 0.5ui re-timing edge phase alignment edge lbw lbw nominal 25k ? r pull up ? + () 5k ? r pull up ? + () ----------------------------------------------------- - =
gennum corporation 522 - 28 - 05 15 of 19 gs1545 fig. 23 pll circuit principles if the signal is not locked, the data transition phase could be anywhere with respect to the internal clock or the quadrature clock. in this case, the normalized filtered sample of the quadrature cl ock will be 0.5. when vco is locked to the incoming data, data will only sample the quadrature clock when it is logic high. the normalized filtered sample quadrature cl ock will be 1.0. we chose a threshold of 0.66 to generate the phase lock signal. because the threshold is lower than 1, it allows jitter to be greater than 0.5ui before the phase lock circuit reads it as ?not phase locked?. input jitter indicator (iji) this signal indicates the amount of excessive jitter (beyond the quadrature clock window 0.5ui), which occurs beyond the quadrature clock window (see figure 23) . all the input data transitions occurring outside the quadrature clock window, will be captured and f iltered by the low pass filter as mentioned in the phase l ock section. the running time average of the ratio of the transitions inside the quadrature clock and outside the quadra ture is available at the plcap/plcap pins. a signal, iji, which is the buffered signal available at the plcap is provided so that loading does not effect the filter circuit. the signal at iji is referenced with the power su pply such that the factor v iji /v cc is a constant over process and power supply for a given input jitter modulation. the iji signal has 10k ? output impedance. figure 24 shows the relationship of the iji signal with respect to the sine wave modulated input jitter. fig. 24 input jitter indicator (typical at t a = 25c) jitter demodulation (dm) the differential jitter demodulation (dm) signal is available at the dm and dm pins. this signal is the phase correction signal of the pll loop, which is amplified and buffered. if the input jitter is modulated, th e pll tracks the jitter if it is within loop bandwidth. to trac k the input jitter, the vco has to be adjusted by the phase detector via the charge pump. thus, the signal which controls the vco contains the information of the input ji tter modulation. the jitter demodulation signal is only valid if the input jitter is less than 0.5uip-p. the dm/dm signals have 10k ? output impedance, which could be low pass filtered with appropriate capacitors to eliminate high frequency noise. dft_v ee should be connected to gnd to activate dm/dm signals. the dm signals can be used as diagnostic tools. assume there is an hdtv sdi source, which contains excessive noise during the horizonta l blanking because of the transient current flowing in the power supply. in order to discover the source of the no ise, one could probe around in-phase clock input data with jitter 0.5ui re-timing edge phase alignment edge quaderature clock plcap signal plcap signal 0.25ui p-p sine wave jitter in ui iji voltage 0.00 4.75 0.15 4.75 0.30 4.75 0.39 4.70 0.45 4.60 0.48 4.50 0.52 4.40 0.55 4.30 0.58 4.20 0.60 4.10 0.63 3.95 iji signal (v) input jitter (ui) 0.00 0.20 0.40 0.60 0.80 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6
gennum corporation 522 - 28 - 05 16 of 19 gs1545 the source board with a low frequency oscilloscope (bandwidth < 20mhz) that is tr iggered with an appropriately filtered dm/dm signal. the true cause of the modulation will be synchronous and will appear as a stationary signal with respect to the dm/dm signal. figure 25 shows an example of such a situation. an hdtv sdi signal is modulated with a modulation signal causing about 0.2ui jitter in figu re 25 (channel 1). the gs1545 receives this signal and locks to it. figure 25 (channel 2) shows the dm signal. notice the wave shape of the dm signal, which is synchronous to the modulating signal. the dm/dm signal could also be used to compare the output jitter of the hdtv signal source. fig. 25 jitter demodulation signal lock logic logic is used to produce the pll_lock signal which is based on the lfs signal and phase lock signal. when there is not any data input, the integrator will charge and eventually saturate at either end. by sensing the saturation of the integrator, it is determi ned that no data is present. if either data is not present or phase lock is low, the lock signal is made low. logic signals are used to acquire the frequency by sweeping the integrator. injecting a current into the summing node of the integrator achieves the sweep. the sweep is disabled once phase lock is asserted. the direction of the sweep is also changed once lfs saturates at either end. bypass the bypass block bypasses the reclocked/mute path of the data whenever a logic low input is applied to the bypass input. in the bypass mode, the mute does not have any effect on the parallel outputs. also, the internal pll still locks to a valid hdtv signal and shows pll_lock. serial output stage the serial output signals ddo, ddo have a nominal voltage of 400mvpp differential, or 200mvpp single ended when terminated with 50 ?. ddo_en the ddo_en enables or disables the serial output driver. to disable the driver, tie ddo_en to v cc . to enable the driver, tie ddo_en to v ee . when disabled, the supply current is reduced by approximately 10ma. a/d a/d is a ttl compatible input pin used to select between the analog or digital input. when a/d is at logic high, the analog input is selected. when a/d is low, the digital input is enabled. cli the voltage output of cli pin is proportional to the amount of cable present at the gs1545 analog input. with 0m of cable (800mv input signal leve ls), the cli output voltage is approximately 3.3v. as the cabl e length increases, the cli voltage decreases providing correlation between the cli voltage and cable length. cli voltage will be a function of the launch voltage and cable type/quality. mcladj the outputs of the gs1545 can be muted when the input signal decreases below a preselected input level. the mcladj pin may be left unconnected for applications where output muting is not required. the use of a carrier detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. carrier detect the cd pin is a ttl compatible output signal. when a carrier is detected at the analog input, the cd pin is pulled low. when a carrier is not detected, the cd will be pulled high. serial to parallel converter the high-speed serial to parallel converter accepts differential clock and data signals from the reclocker core. the s/p core converts this serial output into a 20-bit wide data stream (d[19:0]). note that this data stream is not word aligned or descrambled. it also provides a parallel clock, which is 1/20th the serial clock rate (pclk_out). the outputs of the s/p block are ttl compatible. when the pll loses lock, the parallel clock continues to freewheel. the parallel clock and data outputs were designed for seamless interfaces to the gs1500 and gs1510 deformatters.
gennum corporation 522 - 28 - 05 17 of 19 gs1545 0 ? second pair of bnc shown is for dual footprint option on input connectors j1 nc nc nc nc mclad nc cli nc nc 1 2 3 4 5 6 7 8 9 nc nc cd eqo_v ee nc nc eqo_v cc ddo ddo ddo_v ee ddo_en ddo_v cc nc nc nc nc 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 nc nc nc nc sp_v cc sp_v cc sp_v ee sp_v ee pclk_out pclk_v cc pclk_v ee nc nc 26 27 28 29 30 31 32 33 34 35 36 37 38 65 66 67 68 69 70 72 73 74 75 76 77 78 79 80 81 82 83 84 nc nc nc nc nc nc lfa_v cc lfa lbcont lfa_v ee dm dm lfs nc dft_v ee nc nc nc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 lfs iji nc nc vco nc vco nc plcap nc nc plcap nc pll_lock nc nc nc nc 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 nc nc d10 d11 d12 d13 d14 d15 nc nc d16 d17 d18 d19 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 123 122 124 125 126 127 128 nc nc bypass ddi_v tt nc ddi ddi pd_v cc a/d pdsub_v ee pd_v ee nc nc eqi_v cc nc nc eqi_v ee nc sdi nc sdi nc eqi_v ee nc nc bypass c25 10n c33 47 c32 47 v cc a/d j5 j6 j3 10nh r12 75 r15 75 v cc c17 10n c18 47p c20 47p r13 37.5 bnc_anchor c19 10n r8 15k r17 2k r6 10k v cc v cc c22 10n v cc cd sdo_en c24 47 + c23 47 + j7 j4 pclk d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 v cc c29 10n c30 10n c31 10n (110/112) (19/21) (30-31/32-33) pll_lock vco lfa c27 10n c26 10n c28 1 + c34 1 + c35 10n v cc analog power plane v cc c54 100n c55 10 l10 r111 c53 10 c56 100n v cc main power plane v cc c49 10 c51 10 c50 100n c52 100n v cc digital power plane v cc v cc c64 10 c61 100n r116 0 ? l17 c60 10 c59 100n l8 r19 vco power plane gs1545 l5 nc 71 all resistors in ohms, all capacitors in farads, unless otherwise shown. cli v cc v cc (35/36) c65 10n v cc nc nc 1p5 0 ? 0 ? note that these outputs are not cable drivers typical application circuit
gennum corporation 522 - 28 - 05 18 of 19 gs1545 typical application circuit (continued) application information please refer to the ebhdrx evaluation board documentation for more detailed application and circuit information on using the gs1545 with the gs1500 and gs1510 deformatters. go1515 vco lfa c43 100n c42 10 1 2 3 v cc u2 go1515 4 5 6 7 + 8 vco gnd gnd v cc gnd vctr o/p gnd nc power connect v cc c41 + 10 c44 100n gs1545 lock detect r26 22k q3 led3 r27 150 v cc pll_lock gs1545 cd v cc r28 150 led4 q1 r25 20k cd gs1545 configuration jumpers a/d v cc v cc v cc all resistors in ohms, all capacitors in farads, unless otherwise shown. ddo_en bypass
522 - 28 - 05 19 of 19 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation shinjuku green tower building 27f 6-14-1, nishi shinjuku shinjuku-ku, tokyo 160-0023 japan tel: +81 (03) 3349-5501 fax: +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright may 2000 gennum corporation. all rights reserved. printed in canada. gs1545 package dimensions 23.20 0.25 20.0 0.10 18.50 ref 17.20 0.25 14.0 0.10 12.50 ref 3.00 max 2.80 0.25 1.6 ref 0.30 max radius 0.13 min. radius 0.88 0.15 0.75 min 12 typ 0 - 7 0 -7 0.27 0.08 0.50 bsc 128 pin mqfp all dimensions are in millimetres. revision notes: added lead-free and green information. for latest product information, visit www.gennum.com caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change without notice.

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